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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
DESCRIPTION
The FOD2200 is an optically coupled logic gate that combine an AlGaAs LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. The Electrical and Switching Characteristics of the FOD2200 are guaranteed over the temperature range of 0C to 85C and a VCC range of 4.5 volts to 20 volts. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed optocouplers. Logic signals are transmitted with a maximum propagation delay of 300 nsec. The FOD2200 is useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments.
8 1
8 1
8 1
FEATURES
* 1 kV/s Minimum Common Mode Rejection * Compatible with LSTTL, TTL, and CMOS Logic * Wide VCC Range (4.5 to 20 V) * 2.5 Mbd Guaranteed over Temperature * Low Input Current (1.6 mA) * Three State Output (No Pullup Resistor Required) * Guaranteed Performance from 0C to 85C * Hysteresis * Safety Approvals Pending - UL, CSA, VDE * VISO = 5kVRMS
APPLICATION
* * * * * * * Isolation of High Speed Logic Systems Computer-Peripheral Interfaces Microprocessor System Interfaces Ground Loop Elimination Pulse Transformer Replacement Isolated Buss Driver High Speed Line Receiver
NC 1 ANODE 2 CATHODE 3 NC 4 8 VCC 7 VO 6 VE 5 GND
SHIELD
Schematic
ICC 8 IF + VF - 2 IE 3 SHIELD 6 5 IO 7 VCC
VO VE GND
TRUTH TABLE (Positive Logic)
LED On Off On Off Enable H H L L Output Z Z H L
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
ABSOLUTE MAXIMUM RATINGS (TA = 25C unless otherwise specified)
Parameter Storage Temperature Operating Temperature Lead Solder Temperature (1.6mm below seating plane) EMITTER Peak Transient Input Current (1s PW, 300 pps) Average Forward Input Current Reverse Input Voltage Output Power Dissipation (No derating required up to 85C) DETECTOR Supply Voltage Average Output Current Three State Enable Voltage Output Voltage Output Power Dissipation (No derating required up to 85C) VCC IO VE VO PD 0 to 20 25 -0.5 to 20 -0.5 to 20 150 V mA V V mW IF (PK) IF VR PD 1.0 10 5.0 45 A mA V mW Symbol TSTG TOPR TSOL Value -40 to +125 -40 to +85 260 for 10 sec Units C C C
RECOMMENDED OPERATING CONDITIONS
Parameter Forward Input Current Forward Input Current Supply Voltage, Output Enable Voltage, Low Level Enable Voltage, High Level Operating Temperature Fan Out (TTL load) Symbol IF(ON) IF(OFF) VCC VEL VEH TA N 4.5 0 2.0 0 Min 1.6* Max 5 0.1 20 0.8 20 +85 4 Units mA mA V V V C
*The initial switching threshold is 1.6mA or less. It is recommended that 2.2 mA be used to permit at least a 20% CTR degradation guardband.
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
ELECTRICAL CHARACTERISTICS (TA = 0C to +85C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA,
VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0 mA to 0.1 mA Unless otherwise specified.) See Note 1.
INDIVIDUAL COMPONENT CHARACTERISTICS
Parameter EMITTER Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Input Diode Temperature Coefficient DETECTOR High Level Supply Current Low Level Supply Current Low Level Enable Current High Level Enable Current High Level Enable Voltage Low Level Enable Voltage Test Conditions Symbol Min Typ** 1.40 5.0 60 -1.4 3.5 4.0 4.4 5.2 -0.1 4.5 6.0 6.0 7.5 -0.32 20 100 250 0.8 Max 1.75 1.7 Unit V V pF mV/C (IF = 5 mA) VF TA =25C (IR = 10 A) BVR (Pins 2 & 3) (VF = 0, f = 1 MHz) CIN (IF = 5 mA) VF/TA (IF = 5 mA) VCC = 5.5V (IO = Open, VE = Don't care) VCC = 20V (IF = 0 ) VCC = 5.5V (IO = Open, VE = Don't care) VCC = 20V VE = 0.4 V VE = 2.7 V VE = 5.5 V VE = 20 V ICCH ICCL IEL IEH 0.005 VEH VEL 2.0
mA mA mA A V V
SWITCHING CHARACTERISTICS (TA = 0C to +85C, IF(ON) = 1.6mA to 5mA, IF(OFF) = 0 to 0.1 mA,
VCC = 4.5 to 20V Unless otherwise specified.)
AC Characteristics Propagation Delay Time to Output High Level Propagation Delay Time to Output Low Level Test Conditions Symbol (Note 2, 4) (Fig. 1) With Peaking Capacitor (Note 3, 4) (Fig. 1) With Peaking Capacitor (Note 5) (Fig. 1) (Note 6) (Fig. 1) TPLH TPHL tr tf tPZH tPZL TPHZ TPLZ |CMH| 1000 Min Typ** 120 180 80 25 40 50 95 80 Max 300 300 Unit ns ns ns ns ns ns ns ns V/s
Output Rise Time (10-90%) Output Fall Time (90-10%) Enable Propagation Delay Time (Fig. 2) to Output High Level Enable Propagation Delay Time (Fig. 2) to Output Low Level Disable Propagation Delay Time from Output High Level (Fig. 2) Disable Propagation Delay Time from Output Low Level (Fig. 2) Common Mode (TA =25C) Transient Immunity (IF = 1.6 mA, VOH (Min.) = 2.0 V) |VCM| = 50 V (at Output High Level) VCC = 5V (Note 7)(Fig. 3) Common Mode (TA =25C) Transient Immunity (IF = 0 mA, VOL (Max.) = 0.8 V) |VCM| = 50 V VCC = 5V (Note 8)(Fig. 3) (at Output Low Level) ** Typical values at TA = 25C, VCC = 5V, IF(ON) = 3 mA unless otherwise specified.
(c) 2004 Fairchild Semiconductor Corporation
|CML|
1000
V/s
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
TRANSFER CHARACTERISTICS (TA = 0C to +85C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA,
VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0mA to 0.1mA Unless otherwise specified.) See Note 1.
DC Characteristics Output Leakage Current (VOUT > VCC) Low Level Output Voltage Input Threshold Current Logic High Output Voltage Test Conditions Symbol (VCC = 4.5 V) VO = 5.5V (IF = 5 mA) VO = 20V (VCC = 4.5 V, IF = 0 mA) (VE = 0.4 V, IOL = 6.4 mA) (Note 2) (VCC = 4.5 V, VO = 0.5 V, VE = 0.4 V, IOL = 6.4 mA) IOH = -2.6 mA VO = 0.4 V, VEN = 2 V, IF = 5 mA High Impedance State Output Current VO = 2.4 V, VEN = 2 V, IF = 5 mA VO = 5.5 V, VEN = 2 V, IF = 5 mA VO = 20 V, VEN = 2 V, IF = 5 mA Logic Low Short Circuit Output Current Note 10 Logic High Short Circuit Output Current Note 10 Input Current Hysteresis VO = VCC = 5.5 V, IF = 0 mA VO = VCC = 20 V, IF = 0 mA VCC = 5.5 V, IF = 5 mA, VO = GND VCC = 20 V, IF = 5 mA, VO = GND VCC = 4.5 V IOSL IOSH IHYS 25 40 -10 -25 0.03 IOZH IOHH VOL IFT VOH IOZL 2.4 VCC-1.8 -20 20 100 500 Min Typ** 2.0 2.5 0.33 Max 100 500 0.5 1.6 Unit A V mA V A A A A mA mA mA mA mA
ISOLATION CHARACTERISTICS (TA = -40C to +85C Unless otherwise specified.)
Characteristics Withstand Insulation Test Voltage Resistance (Input to Output) Capacitance (Input to Output) Test Conditions (RH < 50%, TA = 25C) t = 1 min (Note 9) (VI-O = 500 VDC) (Note 9) (VI-O = 0V, f = 1 MHz) (Note 9) Symbol VISO RI-O CI-O Min 5000 1012 0.6 Typ** Max Unit VRMS pF
** Typical values at TA = 25C, VCC = 5V, IF(ON) = 3 mA unless otherwise stated.
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
NOTES
1. The VCC supply to each optoisolator must be bypassed by a 0.1F capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. tPLH - Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse to the 1.3V level on the LOW to HIGH transition of the output voltage pulse. 3. tPHL - Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse to the 1.3V level on the HIGH to LOW transition of the output voltage pulse. 4. When the peaking capacitor is omitted, propagation delay times may increase by 100 ns. 5. tr - Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse. 6. tf - Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse. 7. CMH - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). 8. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e., VOUT < 0.8 V). 9. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together. 10. Duration of output short circuit time should not exceed 10 ms.
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
PULSE GEN. tr = tf = 5 ns f = 100 kHz 10 % DUTY CYCLE VO = 5 V IF INPUT MONITORING NODE R1 VCC OUTPUT VO MONITORING NODE
FOD2200
1 2 3
5V D1 619
VCC 8
7 6
C2 = 15 pF 5 k
D2 D3 D4
4 C1 = 120 pF
GND 5
THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C1 AND C2. 2.15 k 1.10 k 681 RI 5 mA IF (ON) 1.6 mA 3 mA ALL DIODES ARE 1N916 OR 1N3064.
INPUT IF
IF (ON) 50 % IF (ON) 0 mA tPLH tPHL
OUTPUT VO
VOH 1.3 V VOL
Fig. 1. T Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
CL= 15 pF INCLUDING PROBE PULSE AND JIG CAPACITANCES. GENERATOR VCC ZO = 50 tr = tf = 5 ns VO FOD2200
1
+5 V
S1 D1 619
VCC 8
7 6
IF
2 3 4
CL 5 k
D2 D3 D4 S2
GND 5
INPUT VC MONITORING NODE D1-4 ARE 1N916 OR 1N3064.
INPUT VE
tPZL 1.3 V
tPLZ 0.5 V 0.5 V 1.3 V 0V tPHZ
3.0 V 1.3 V 0V S1 AND S2 CLOSED VOL VOH 1.5 V S1 AND S2 CLOSED
OUTPUT S1 CLOSED VO S2 OPEN tPZH OUTPUT VO S1 OPEN S2 CLOSED
Fig. 2. T Test Circuit and Waveforms for tPHZ, tPZH, tPLZ, and tPZL
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
FOD2200
A B 1 2 3
VCC OUTPUT VO MONITORING NODE 0.1 F BYPASS
VCC 8
7 6 5
RIN
VFF
4
GND VCM -
PULSE GENERATOR +
VCM 0V VOH OUTPUT VO VOL * SEE NOTE 6.
50 V SWITCH AT A: IF = 1.6 mA VO (MIN.)* SWITCH AT B: IF = 0 mA VO (MAX.)*
Fig. 3. Test Circuit and Typical Waveforms for Common Mode Transient Immunity
VCC1 (+5 V)
VCC1 (+5 V) 1.1 k 120 pF FOD2200 1 2 DATA INPUT TOTEM POLE OUTPUT GATE
1 2
120 pF (OPTIONAL*) 1.1 k
1 2
VCC2 (+5 V) DATA OUTPUT
VCC2 (4.5 TO 20 V)
FOD2200 VCC 8
7 6
VCC 8 7 6 GND 5
RL
CMOS
DATA OUTPUT
3 TTL OR LSTTL 4
UP TO 16 LSTTL LOADS OR 4 TTL LOADS
DATA INPUT TOTEM POLE OUTPUT GATE
1
3
TTL OR LSTTL
4
GND
5
VCC2 5V 10 V 15 V 20 V
RL 1.1 K 2.37 K 3.83 K 5.11 K
2
Figure 4. Recommended LSTTL to LSTTL Circuit.
Figure 5. LSTTL to CMOS Interface Circuit.
VCC (+5 V)
VCC1 (+5 V) 1.1 k FOD2200
120 pF (OPTIONAL*) 1.1 k FOD2200
1 2
1
DATA INPUT TTL OR LSTTL D1
VCC 8
VCC 8
7 6
2 3 4
GND
7
4.7 k
6 5
DATA INPUT OPEN COLLECTOR GATE
3
TTL OR LSTTL
4
GND
5
D1 (1N4150) REQUIRED FOR ACTIVE PULL-UP DRIVER.
Figure 6. Recommended LED Drive Circuit.
Figure 7. Series LED Drive with Open Collector Gate (4.7 k Resistor Shunts IOH from the LED).
*The 120pF capacitor may be omitted in applications where 500ns propagation delay is sufficient.
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
TYPICAL PERFORMANCE CURVES
Figure 8. Input Forward Current vs Forward Voltage
100 5 VCC = 4.5V TA = 25C IF - Forward Current (mA) TA = 85C 1 TA = 70C TA = 25C 0.1 TA = 0C TA = -40C VO - Output Voltage (V) 10 4
Figure 9. Output Voltage vs. Input Forward Current
3
IO = -2.6mA
2 IF(OFF) 1 IO = 6.4mA IF(ON)
0.01
0.001 0.9 1.0 1.1 VF 1.2 1.3 1.4 1.5 - Forward Voltage (V) 1.6 1.7
0 0.0 0.2 0.4 0.6 0.8 IF - Input Forward Current (mA) 1.0 1.2
Figure 10. Input Threshold Current vs. Ambient Temperature
1.2 VCC = 5V, 20V Input Current Threshold (mA) 1.0 0.8 IF(ON) 0.6 0.4 0.2 0.0 -40 IF(OFF) VOL - Logic Low Output Voltage (V)
Figure 11. Logic Low Output Voltage vs. Ambient Temperature
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 VCC = 4.5V IF = 0 mA IO = 6.4 mA
-20
0 20 40 60 TA - Ambient Temperature (C)
80
100
-40
-20
0 20 40 60 TA - Ambient Temperature (C)
80
100
Figure 12. Logic High Output Voltage vs. Supply Voltage
20 VOH - Logic High Output Voltage (V) IO = -2.6 mA TA = 25C IF IF (ON)
Figure 13. Logic High Output Current vs. Ambient Temperature
0 IOH - Logic High Output Current (mA) -1 -2 VO = 2.7V -3 -4 VO = 2.4V -5 -6 -7 -40 VCC = 4.5V IF = 5 mA
16
12
8
4
0 0 4 8 12 VCC - Supply Voltage (V) 16 20
-20
0 20 40 60 TA - Ambient Temperature (C)
80
100
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
TYPICAL PERFORMANCE CURVES
Figure 14. Propagation Delay vs Ambient Temperature
260 tP - Propagation Delay (s) VCC = 5V C1 (120 pF) Peaking Capacitor Is Used. See Figure 1. 200 VCC = 5V IF = 1.6mA tf, tr - Rise, Fall Time (s) 160
Figure 15. Rise, Fall Time vs Ambient Temperature
220
180
tPHL, IF = 5 mA tPHL, IF = 3 mA tPHL, IF = 1.6 mA
120 tr
140
80
100
tPLH, IF = 1.6 - 5 mA
40
tf
60 -40 -20 0 20 40 60 TA - Ambient Temperature (C) 80 100
0 -40 -20 0 20 40 60 TA - Ambient Temperature (C) 80 100
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
Package Dimensions (Through Hole) Package Dimensions (0.4"Lead Spacing)
PIN 1 ID.
4 3 2 1
PIN 1 ID.
4
3
2
1
0.270 (6.86) 0.250 (6.35)
5 6 7 8
0.270 (6.86) 0.250 (6.35)
0.390 (9.91) 0.370 (9.40)
5
6
7
8
SEATING PLANE
SEATING PLANE
0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.020 (0.51) MIN
0.390 (9.91) 0.370 (9.40) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.004 (0.10) MIN
0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 15 MAX 0.300 (7.62) TYP
0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 0 to 15 0.400 (10.16) TYP
Package Dimensions (Surface Mount)
0.390 (9.91) 0.370 (9.40)
4 3 2 1
8 - Pin Dip
PIN 1 ID.
0.070 (1.78)
0.270 (6.86) 0.250 (6.35)
0.060 (1.52)
5 6 7 8
0.070 (1.78) 0.045 (1.14) 0.020 (0.51) MIN
0.300 (7.62) TYP 0.016 (0.41) 0.008 (0.20)
0.100 (2.54) 0.295 (7.49) 0.415 (10.54) 0.030 (0.76)
0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP Lead Coplanarity : 0.004 (0.10) MAX
0.045 [1.14] 0.315 (8.00) MIN 0.405 (10.30) MIN
NOTE All dimensions are in inches (millimeters)
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
Carrier Tape Specifications
K0
t
P0
P2
D0 E
A0 W1 B0
F W
d
User Direction of Feed
P
D1
Description Tape Width Tape Thickness Sprocket Hole Pitch Sprocket Hole Diameter Sprocket Hole Location Pocket Location Pocket Pitch Pocket Dimensions Cover Tape Width Cover Tape Thickness Max. Component Rotation or Tilt Min. Bending Radius
Symbol W t P0 D0 E F P2 P A0 B0 K0 W1 d R
Dimension in mm 16.0 0.3 0.30 0.05 4.0 0.1 1.55 0.05 1.75 0.10 7.5 0.1 4.0 0.1 12.0 0.1 10.30 0.20 10.30 0.20 4.90 0.20 1.6 0.1 0.1 max 10 30
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
ORDERING INFORMATION Example: FOD2200 X
X Packaging Option S: Surface Mount Lead Bend SD: Surface Mount, Tape and Reel T: 0.4" Lead Spacing V: VDE 0884 TV: VDE 0884, 0.4" Lead Spacing SV: VDE 0884, Surface Mount SDV: VDE 0884, Surface Mount, Tape and Reel
MARKING INFORMATION
1
2200 V
3 4
2 6
XX YY B
5
Definitions
1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option - See order entry table) Two digit year code, e.g., `03' Two digit work week ranging from `01' to `53' Assembly package code
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
Reflow Profile
300 Temperature (C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 260 C peak
245 C, 10-30 s
Time above 183C, <160 sec Ramp up = 2-10C/sec 3 3.5 4 4.5
Time (Minute) * Peak reflow temperature: 260 C (package surface temperature) * Time of temperature higher than 183 C for 160 seconds or less * One time soldering reflow is recommended
(c) 2004 Fairchild Semiconductor Corporation
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LOW INPUT CURRENT LOGIC GATE OPTOCOUPLERS
FOD2200
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) 2004 Fairchild Semiconductor Corporation
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